1. Field of the Disclosure
The present disclosure relates to an array substrate, and particularly, an array substrate including an oxide semiconductor layer and a method of fabricating the same.
2. Discussion of the Related Art
Recently, facing an information laden society, a field of processing and displaying mass information has rapidly advanced, and many kinds of flat display devices are developed and highly favored.
As the flat display devices, liquid crystal display devices (LCDs), plasma display panel device (PDPs), field emission display devices (FEDs), electroluminescent display device (ELDs), organic light emitting diodes (OLEDs) are used. These display devices have advantages of thin profile, lightweight, and low power consumption, and are rapidly substituted for conventional cathode ray tubes (CRTs).
The flat display device typically includes an array substrate where a thin film transistor (TFT) as a switching element turning on/off a pixel is formed in each pixel.
For the purpose of explanation, an LCD most widely used among the flat display devices is illustrated in connection with the figures. The LCD has advantages of high performance in displaying moving images and high contrast ratio and is used for laptop computers, desktop monitors, TVs, or the like.
FIG. 1 is a cross-sectional view illustrating an array substrate for an LCD according to the related art.
Referring to FIG. 1, the array substrate 10 includes a plurality of gate lines on a substrate 1, and a plurality of data lines 15 crossing the gate lines to define a plurality of pixel regions P.
A TFT T is formed at a switching region near a crossing portion of the gate line and the data line 15. A common electrode 21 and a pixel electrode 25 are also formed at a display region and used in displaying an image.
The TFT T includes a gate electrode 3, a gate insulating layer 5, an oxide semiconductor layer 7, and source and drain electrodes 11 and 13, respectively.
An etch stopper 9 is formed between the source and drain electrodes 11 and 13 and the oxide semiconductor layer 7, and includes semiconductor contact holes 9a exposing each of both side portions of the oxide semiconductor layer 7. The source and drain electrodes 11 and 13 contact the respective side portions of the oxide semiconductor layer 7 through the respective semiconductor contact holes 9a. 
A first passivation layer 17 is formed on the entire surface of the substrate 1 having the TFT T, and a second passivation layer 19 is formed on the first passivation layer. The common electrode 21 is formed on the second passivation layer 19 corresponding to the entire display region and is made of a transparent conductive material.
A third passivation layer 23 is formed on the common electrode 21. The first to third passivation layers 17, 19, and 23 include a drain contact hole 13a exposing the drain electrode 13.
The pixel electrode 25 is formed on the third passivation layer 23 in each pixel region P and contacts the drain electrode 13 through the drain contact hole 13a. 
The pixel electrode 25 includes a plurality of bar-shaped openings OP therein, and thus, produces a fringe electric field along with the common electrode 21 therebelow.
The above-described array substrate 10 is used for a fringe field switching mode LCD.
In the array substrate 10, the oxide semiconductor layer 7 is reacted with hydrogen gas when depositing the first passivation layer 17, and thus, hydrogen atoms act as a carrier in the oxide semiconductor layer 7. This causes a problem in that the oxide semiconductor layer 7 then changes into a conductor. Further, the semiconductor layer 7 has an increase in propensity for oxygen vacancy generation due to ionic bonds, and this causes an increase of electron density.
Particularly, when forming the source and drain electrodes 11 and 13, oxygen concentration at a back channel region after dry-etching or wet-etching remarkably decreases. Thus, the oxide semiconductor layer 7 changes into a conductor, and caused increased leakage in the TFT.
To solve the above problems, the etch stopper 9 is formed so that the oxide semiconductor layer 7 is not exposed to hydrogen gas during deposition of the first passivation layer 17. However, this causes problems of more complicated design and processes with an associated increase of production costs.
Further, defect frequency increases, and thus, production efficiency is reduced.
Particularly, metal wire such as the source and drain electrodes is formed using low-resistance metal materials such as copper (Cu) in order to achieve display devices having large size and high resolution, and in this case, oxidation of metal wire is caused due to a high oxidation property of Cu and thus, leakage current occurs from the TFT. Therefore, reliability of the TFT element is reduced.